 THEORY OF OPERATION
The simplified block diagram to the right illustrates the basic concept of the Model LDPC16 Elastic Buffer. The LDPC16 uses a "fall-through" stack to delay receive data as necessary to achieve phase coherence. The phaser initially loads the stack to the half-full position. When the receive clock gates data into the top of the stack, it falls through to the first empty slot. Meanwhile, data is being gated out of the stack at a rate determined by the master clock. If the receive clock drifts faster than the master clock, the stack expands; if the receive clock drifts slower than the master clock, the stack contracts. Regardless of whether the stack is expanding or contracting, the master clock gates data out at a consistent rate. Therefore, phase coherence between two or more different channels can be achieved simply by bringing the data in through separate buffers and using the same master clock to gate the data out of each buffer.
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 MODEL LDP4HI INTERFACE CARD
Each LDPC16 chassis requires one LDP4HI Interface Card. This card provides the input/output interfaces for up to 2.5 MHz. Jumper options on the LDP4HI permit setting the reference clock, data, and load clock inputs to accept either a balanced or an unbalanced input signal. The "Recenter in Process" output signal may be strapped to provide either a high (+6 volt) output or a low (-6 volt) output. The buffer circuitry in the LDPC16 will be automatically recentered when a "buffer full" or "buffer empty" condition exists. The buffer may also be recentered at any time through an external control signal on the LDP4HI Interface Card. The output signal of the LDP4HI is switch selectable to provide either a MIL-188 Mark (negative level) or an EIA Mark (positive level). The LDP4HI is installed in card position #2 of LDPC16 chassis.
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 MODEL LDP4 BUFFER CARD
The buffer capacity of Model LDP16 is determined by the number of Model LDP4 buffer cards (1 to 16) installed in the chassis. Each LDP4 buffer card provides a total capacity of 2,048 bits (+1,024 bits and -1,024 bits). An LDPC16 chassis equipped with the maximum number (16) of LDP4 buffer cards would have a total buffer capacity of 16 x 2,048 or 32,768 bits (+16,384 and -16,384). The first LDP4 buffer card is located in card position #3 of the LDPC16 chassis. Each successive LDP4 buffer card is installed to the right of the previous one. The LDP4 buffer card contains no jumpers or switches.
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 MODEL LDPC16 CHASSIS
The VERSITRON elastic buffer is housed in an LDPC16 chassis. It measure 19.0" wide x 3.5" high x 18.0" deep and mounts in a standard 19-inch rack. The Model LDP4HI Interface Card and Model LDP4 Buffer Cards slide into the chassis enclosure and plug into the motherboard connectors in the rear. A power supply assembly is located at the rear of the chassis. The clock and data interface connections with the LDPC16 are made through five Twinax connectors J1 thru J5 on the rear panel. A DB9 connector provides an interface for recentering control signals.
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POWER SYSTEM
The LDPC16 contains an integral power supply operating at 115 volts AC with less than 1 Amp maximum current. A Power Supply Monitor Card, installed in card position #1 of the chassis, provides LED status of power to the LDP4HI Interface Card and LDP4 Buffer Cards.
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The status indicators of the LDPC16 Elastic Buffer are visible through the front panel of the unit and provide a continuous display of the number of bits present in the buffer. The top group of lights indicate how close the buffer is to being empty. Increments of 256 bits are used to indicate the buffer being filled or emptied.
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PHYSICAL CHARACTERISTICS
LDPC16 Chassis: 19.0" wide x 3.5" high x 18.0" deep.
LDP4HI Interface Card: 0.5" wide x 2.5" high x 12.25" deep.
The LDPC16 chassis weighs approximately 41 lb (18.6 kg) fully loaded and 32 lb (14.5 kg) empty.
Power requirements: 115 VOLTS AC, ±10%, 60 Hz. Less than 1 Amp maximum current.
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